Bottom line: IBM doubles transistor density through vertical stacking at 0.7 nanometers and expects up to 70 percent energy savings — production readiness in approximately five years.
IBM has developed a new transistor technology in the sub-1-nanometer range at its semiconductor research center in Albany, enabling nearly 100 billion transistors on the surface area of a fingernail. The innovation doubles the transistor density compared to IBM’s 2-nanometer chips from 2021.
The new technology operates at a structural size of 0.7 nanometers (7 ångströms) and is based on a transistor architecture called Nanostack. This three-dimensional design stacks transistors vertically on top of each other and offsets them to use space on silicon more efficiently. The nanosheet-based construction represents a shift from conventionally horizontal to spatially stacked design.
Technical reports predict for the Nanostack architecture a boost in computing performance of up to 50 percent or a reduction in energy demand of up to 70 percent compared to the 2-nanometer generation. Measurements at the VLSI 2026 conference also showed static RAM memory scaling of 40 percent. This makes the technology particularly relevant for the infrastructure of generative language models and cloud data centers.
For further development, IBM is using an extreme ultraviolet lithography system with high numerical aperture from ASML at its Albany facility. In tool development, the company cooperates with Lam Research, Tokyo Electron, and Screen Semiconductor Solutions. IBM expects the Nanostack technology to be production-ready within five years. Additionally, IBM is establishing the independent facility Anderson to support quantum wafer manufacturing as a specialized quantum foundry.
Source: www.it-daily.net · Published June 26, 2026
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